FunCPU - Testing ALU and Register modules

The vast majority of FunCPU has been completed. Static modules (ALU and registers) are being verified now. The image below shows three modules interconnected. The upportmost is the test module. In the middle one can see the register file, and on the bottom the ALU can be found.

Once static function has been verified, the micro-sequence can implemented and connected to these modules. Numerous tests are to be performed to check if everything is working as expected. Applying different setup conditions defined by the 6 DIP switches mounted on the test-board (note: an additional bus must have been added to the test module.) I can check each register and ALU function by observing the ALU or register output connected to the LED bars on the test module. 

The following basic cases have been identified:

• RI_SET (this is tricky, as first DI must be incremented, then cleared)
• DI_CLR_, DI_SET_, DI_INC - clear, set and increment DI respectively.
• SI_CLR_, SI_INC - clear and increment SI respectively.
• V_CLR_, V_SET - clear and set V respectively.
• S_SET, S_CLR - again for set and clear operation executed on S.
• SCZ_SET, SCZ_CLR - same for the SCZ register.
• AC_INC, AC_SET - increment and set argument counter respectively. Special care must be taken to check the working of argument counter flag.
• FI_SET_, FI_INC - setting and incrementing of function index register.
• V register must be tested against different ALU setup (decrement, identity and increment modes).
• Address multiplexer should generate address signals as designed one of the following sources: SI, DI, FI, SI+V'. The last one is an integration test, involving ALU operations.

The following buses will be used for input for register module:

• B10 to provide power supply, classification information and raw 8 bit data.
• B11 to supply most of the control signals (including the two-phase clock) to be generated by the micro-sequencer.
• B12 to transfer additional control information also determined by the micro-program.

The following buses will supply input for the test module:

• B9 - transferring the 7 bit result (MSB is preserved).
• B13 - displaying the 8 bit address.
• B14 - supplying status, classification and argument counter zero flag to micro-sequencer.
• B16 - containing the full 8 bit result of the ALU operation. 

In addition to that, of course register and ALU modules are interconnected as the image above also reveals.

FunCPU - Arithmetic Logic Unit

The ALU module is very simple and straightforward. It is mounted together with the control board encoding logic on a single board. It performs a simple addition operation on the two operands as described in the following table. The two selector bits define the two input sources.

ALU selector	Input A	Input B	Carry	Result	Usage
00	0000 0000 (0)	V	0	V	Identity / copy
01	AC	V’	0	AC+V’	Argument counting Only four bit value is used
10	1111 1110 (-2)	V	0	V-2	Used to set AC to 1 argument, provided that V is zero beforehand
11	SI	V’	0	SI+V’	Argument binding
00	0000 0000 (0)	V	1	V+1	Increment
01	AC	V’	1	*AC+V’+1
10	1111 1110 (-2)	V	1	V-1	Decrement
11	SI	V’	1	*SI+V’+1

*these combinations are actually not used.
where V’ denotes 1111 11 V(1) V(0), where V(1) and V(0) are the two least significant bits of V.

Notice that the ALU is able to generate V (identity), V-1 (decrement), V+1 (increment) and V-2 based on the V value.

Please also observe that since this is a 7-bit CPU, it is not desirable to go out of the seven bit range. In other words, (without the tag interpretation) when V is holding a constant it cannot go beyond the range of 0..127 no matter if it is incremented or decremented. Therefore when storing the modified V value (here we mean solely V-1, V+1, but not V’) to the expression cell as defined by the destination register, the original most significant bit of the V register is fed back along with the possibly modified 7 bit part of the ALU result. This way the highest bit is always reserved and the actual constant part of the result value must lie in the 7 bit range.

Partially, in line with the aforementioned, the content of V register is not directly connected to the databus, instead, the ALU output (except for the MSB, which is coming from the V register) is released to the databus.

Input sources are mapped by six multiplexers. Four 74HC153s are utilized to select among four sources (SI, AC, 0, -2), and two 74HC157s are used to select between V and V'. The outputs of these multiplexers are fed to two 4008s to perform the 8 bit addition. 

Bus 15 connects register and ALU modules transferring the following signals to the ALU:

V7	V6	V5	V4	V3	V2	V1	V0
SI7	SI6	SI5	SI4	SI3	SI2	SI1	SI1

Bus 16 supplies the full 8 bit ALU result to the register module. This value is used in the course of argument binding.

R7	R6	R5	R4	R3	R2	R1	R0

Bus 9 has similar content, with a different arragnement. It transfers signal from the ALU to the RAM module. 

		R6	R4	R2	R0
		V7	R5	R3	R1

Bus 17 provides the signals to the ALU coming from the register modules as depicted in the table below.

ALU_A	ALU_B	AC3	AC2	AC1	AC0	C	PWR
GND

 Other buses are dedicated to signals related to keyboard processing. These are as follows:

Bus 8 is feeding RAM module with the encoded 8 bit data as defined by the user interface on the control board.

		D6	D4	D2	D0		PWR
GND		D7	D5	D3	D1

Bus 2 is a two way bus, accepting values from the control board (D0..D7) and also telling the control board what datalines can be active in a particular setup (i.e. when hotkeys are pressed) (DE0, DE1, DE6, DE7).

	DE6	D6	D4	D2	D0	DE0	PWR
GND	DE7	D7	D5	D3	D1	DE1

Finally, bus 3 accepts hot key signals from control board. Based on this information along with the 8 bit data determined by the 8 toggle switches (coming via the bus 2), the actual 8 bit data is generated, and then  transferred in bus 8 to the RAM.

	ZERO	EOX	ARG	INC	IF	DEC	PWR
GND