FunCPU - Testing ALU and Register modules

The vast majority of FunCPU has been completed. Static modules (ALU and registers) are being verified now. The image below shows three modules interconnected. The upportmost is the test module. In the middle one can see the register file, and on the bottom the ALU can be found.

Once static function has been verified, the micro-sequence can implemented and connected to these modules. Numerous tests are to be performed to check if everything is working as expected. Applying different setup conditions defined by the 6 DIP switches mounted on the test-board (note: an additional bus must have been added to the test module.) I can check each register and ALU function by observing the ALU or register output connected to the LED bars on the test module. 

The following basic cases have been identified:

• RI_SET (this is tricky, as first DI must be incremented, then cleared)
• DI_CLR_, DI_SET_, DI_INC - clear, set and increment DI respectively.
• SI_CLR_, SI_INC - clear and increment SI respectively.
• V_CLR_, V_SET - clear and set V respectively.
• S_SET, S_CLR - again for set and clear operation executed on S.
• SCZ_SET, SCZ_CLR - same for the SCZ register.
• AC_INC, AC_SET - increment and set argument counter respectively. Special care must be taken to check the working of argument counter flag.
• FI_SET_, FI_INC - setting and incrementing of function index register.
• V register must be tested against different ALU setup (decrement, identity and increment modes).
• Address multiplexer should generate address signals as designed one of the following sources: SI, DI, FI, SI+V'. The last one is an integration test, involving ALU operations.

The following buses will be used for input for register module:

• B10 to provide power supply, classification information and raw 8 bit data.
• B11 to supply most of the control signals (including the two-phase clock) to be generated by the micro-sequencer.
• B12 to transfer additional control information also determined by the micro-program.

The following buses will supply input for the test module:

• B9 - transferring the 7 bit result (MSB is preserved).
• B13 - displaying the 8 bit address.
• B14 - supplying status, classification and argument counter zero flag to micro-sequencer.
• B16 - containing the full 8 bit result of the ALU operation. 

In addition to that, of course register and ALU modules are interconnected as the image above also reveals.

FunCPU - Test Module

Below a simple tester module is depicted. It is designed to facilitate the testing of other modules. 

It has one incoming databus of 16 bit width. Each of the lower eight Leds of the two ten segment Led bars corresponds to one bit in the databus. The upper two Leds of the led display on the left hand side, are as follows:
- The uppermost Led should be on, whenever the most significant bit of the left outcoming databus is connected to the ground.
- The Led below is on to denote that the least significant bit of the same outcoming databus is connected to the power supply.

The two uppermost bits of the Led bar on the right hand side indicates whether we are in clock phase 1 or 2.

The content of the outcoming databus on the left hand side can be manipulated with the two red DIP switches. This bus may also be used to provide power supply to other modules linked to the tester. In such case, the switches designated with the plus and minus signs should be set to their respective position. Recall, this can be checked by looking at the status Leds of the left hand side Led bar.

The data on the other bus on the right hand side can also be given with the 2 Dip switches (one blue and one red). There are however, two special bits on this bus. Bit 10 and 16 represents Clock 1 and Clock 2 respectively. All the other bits can be used and set arbitrary.

The red button next to the 74Hc14 Schmitt trigger is used to move from clock phase 1 (i.e. Clock 1) to clock phase 2 (i.e. Clock 2).

I hope that with this very simple module I will be able to test - among others - the register module, which is planned to be implemented next.